FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
db56c938bf Replace generate with assign 2019-12-17 00:09:38 -08:00
Alex Forencich
554e0a5380 Convert generated ip_arb_mux to verilog parametrized module 2018-11-01 00:40:09 -07:00