FPGA/verilog-ethernet
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515 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
25d1b373cc Use don't care bits 2018-06-14 15:20:20 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00
Alex Forencich
4474181549 Rework UDP datapath modules to separate output register 2014-10-28 01:55:29 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00