FPGA/verilog-ethernet
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115 Commits 1 Branch 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0a79f24d3c Do not reset datapath registers in crosspoint switch 2015-11-08 17:27:13 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
63f6e96492 Add tuser signal to crosspoint module 2014-11-21 01:07:02 -08:00
Alex Forencich
aafacb372e Trim trailing spaces 2014-11-12 15:32:05 -08:00
Alex Forencich
a28a534bff Add AXI stream crosspoint module and testbench 2014-11-12 01:54:31 -08:00