FPGA/verilog-ethernet
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585 Commits 1 Branch 0 Tags
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13 Commits

Author SHA1 Message Date
Alex Forencich
ad8828d5b7 Update FIFO instances 2018-10-30 11:58:06 -07:00
Alex Forencich
fea477db09 Add unused ports 2018-06-11 16:36:44 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
8ff4312601 Update MAC modules to use new modules 2017-05-31 18:37:33 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
08afe3a5d2 Synchronize MAC status signals 2015-10-09 22:51:55 -07:00
Alex Forencich
55071645fd Update async FIFO instances 2015-10-09 22:35:25 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
16fec34ddc Default FIFO size at least 2 MTU (3000 bytes) 2015-05-08 01:44:55 -07:00
Alex Forencich
73bebaba46 Add FIFO wrapper for gigabit MAC module 2015-05-07 23:45:30 -07:00