FPGA/verilog-ethernet
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527 Commits 1 Branch 0 Tags
Commit Graph

122 Commits

Author SHA1 Message Date
Alex Forencich
b6c8cc7125 Append termination control character 2018-11-10 18:16:30 -08:00
Alex Forencich
0159376cda Simplify IFG count handling 2018-11-10 17:35:31 -08:00
Alex Forencich
d59a0553bd Change start character handling 2018-11-09 16:51:54 -08:00
Alex Forencich
261ad46a8a Add enable signals to xgmii model 2018-11-09 16:47:19 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
b3f50ac2c7 Fix comments 2018-11-02 00:40:15 -07:00
Alex Forencich
98fc042489 Convert generated udp_demux to verilog parametrized module 2018-11-02 00:39:52 -07:00
Alex Forencich
81e9aa0c77 Convert generated ip_demux to verilog parametrized module 2018-11-02 00:25:23 -07:00
Alex Forencich
18c4214edb Convert generated eth_demux to verilog parametrized module 2018-11-02 00:23:31 -07:00
Alex Forencich
470ab887d9 Update mux instances 2018-11-01 00:59:14 -07:00
Alex Forencich
fea1186f57 Convert generated udp_arb_mux to verilog parametrized module 2018-11-01 00:48:26 -07:00
Alex Forencich
554e0a5380 Convert generated ip_arb_mux to verilog parametrized module 2018-11-01 00:40:09 -07:00
Alex Forencich
96cefbe0c1 Convert generated eth_arb_mux to verilog parametrized module 2018-10-31 21:42:28 -07:00
Alex Forencich
67025121ab Convert generated udp_mux to verilog parametrized module 2018-10-31 18:09:44 -07:00
Alex Forencich
f20312b199 Convert generated ip_mux to verilog parametrized module 2018-10-31 18:08:39 -07:00
Alex Forencich
d28d459d70 Convert generated eth_mux to verilog parametrized module 2018-10-31 15:48:12 -07:00
Alex Forencich
68abccd0a1 Workaround for MyHDL race condition 2018-10-31 13:42:33 -07:00
Alex Forencich
c08026277e Fix source pause logic 2018-10-31 13:42:08 -07:00
Alex Forencich
733044b0df Work around MyHDL sync race condition 2018-10-30 11:59:09 -07:00
Alex Forencich
20017c04b9 Work around MyHDL cosimulation race condition 2018-10-30 11:58:53 -07:00
Alex Forencich
ad8828d5b7 Update FIFO instances 2018-10-30 11:58:06 -07:00
Alex Forencich
fe0bf3b7c6 Remove old modules 2018-10-24 01:08:27 -07:00
Alex Forencich
0aca4c7dcc Update 10G MAC to use new modules 2018-10-24 00:54:41 -07:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00
Alex Forencich
fbe698ebb7 Update Ethernet MAC testbenches 2018-10-19 15:31:47 -07:00
Alex Forencich
2e9602b5b4 Update testbenches to use wait 2018-07-02 18:20:07 -07:00
Alex Forencich
65c64588a6 More endpoint updates 2018-07-02 16:33:13 -07:00
Alex Forencich
63f9bbeced Update endpoints 2018-07-02 13:20:49 -07:00
Alex Forencich
5b7646ccda Rework ARP subsystem 2018-06-18 13:59:58 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
a3b5d5d167 Update RGMII PHY interface and add RGMII MAC wrappers 2017-05-31 18:40:49 -07:00
Alex Forencich
bb9e789645 Update GMII PHY interface and add GMII MAC wrappers 2017-05-31 18:40:18 -07:00
Alex Forencich
8ff4312601 Update MAC modules to use new modules 2017-05-31 18:37:33 -07:00
Alex Forencich
817e7c2667 Add AXI stream GMII RX and TX modules and testbenches 2017-05-31 16:11:20 -07:00
Alex Forencich
b0a4448e69 Add clk_enable and mii_select inputs to GMII and RGMII endpoints 2017-05-31 16:08:05 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
d5928ee776 Trim UDP and IP payloads to proper length 2016-10-05 17:33:05 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
4e522e52af Clean up endpoint modules 2016-09-30 22:02:29 -07:00
Alex Forencich
0b6614e8d4 Add UDP checksum generator modules and testbenches 2016-09-30 21:59:04 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
c34a9c2197 Add 32 bit XGMII support 2016-07-19 19:59:47 -07:00
Alex Forencich
7d7cba0838 Add bus width checks 2016-07-19 16:21:15 -07:00
Alex Forencich
a430e4463e Add RGMII endpoint and PHY interface module 2016-06-29 06:13:46 -07:00
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
8b762a6009 Add asserts to check for orphaned payloads 2015-05-08 21:25:37 -07:00