FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
527 Commits 1 Branch 0 Tags
Commit Graph

527 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
d1ed1528b5 Update FIFO instance, rename ports 2018-10-25 10:15:16 -07:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports 2018-10-24 23:16:06 -07:00
Alex Forencich
3d2efef93a Update readme 2018-10-24 22:25:02 -07:00
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
3bbf8524d6 Compute DEST_WIDTH 2018-10-24 22:21:31 -07:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
145ea2c40c Connect arbiter parameters to top level 2018-10-24 21:09:00 -07:00
Alex Forencich
2bf15706cd Convert generated mux to verilog parametrized mux 2018-10-24 18:23:14 -07:00
Alex Forencich
029d1fa06f Fix loop count variable scoping issue 2018-10-24 17:58:39 -07:00
Alex Forencich
fc6c07e5f9 Convert generated frame joiner to verilog parametrized frame joiner 2018-10-24 17:07:22 -07:00
Alex Forencich
fd7f65d5ad Convert generated switch to verilog parametrized switch 2018-10-24 16:12:56 -07:00
Alex Forencich
631147069f Rename ports and add reg_type parameter to axis_register 2018-10-24 14:35:08 -07:00
Alex Forencich
940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux 2018-10-24 13:49:17 -07:00
Alex Forencich
fe77db822d Convert generated crosspoint to verilog parametrized crosspoint 2018-10-24 13:44:39 -07:00
Alex Forencich
2c5679ff6a Update readme 2018-10-24 10:59:02 -07:00
Alex Forencich
4c711b8c7a Update readme 2018-10-24 01:19:26 -07:00
Alex Forencich
fe0bf3b7c6 Remove old modules 2018-10-24 01:08:27 -07:00
Alex Forencich
00dc50826d Update example designs 2018-10-24 01:03:44 -07:00
Alex Forencich
0aca4c7dcc Update 10G MAC to use new modules 2018-10-24 00:54:41 -07:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00
Alex Forencich
030fe90bf5 Fix example design testbench 2018-10-19 15:33:25 -07:00
Alex Forencich
fbe698ebb7 Update Ethernet MAC testbenches 2018-10-19 15:31:47 -07:00
Alex Forencich
5e12f97518 MAC optimizations 2018-10-19 15:24:33 -07:00
Alex Forencich
553547f661 Fix test naming 2018-09-09 13:52:13 -07:00
Alex Forencich
becfbf4425 When pausing the AXI stream model, do not drop tvalid if it is asserted and waiting for tready to be asserted 2018-08-15 00:11:39 -07:00
Alex Forencich
14d8819cd3 merged changes in axis 2018-08-09 18:41:34 -07:00
Alex Forencich
8e5ec36ced Optimize axis_arb_mux and improve latency 2018-08-09 18:40:50 -07:00
Alex Forencich
7a879aec1c Remove extra registers 2018-08-09 18:38:41 -07:00
Alex Forencich
b5ec1c4a30 merged changes in axis 2018-08-09 11:24:21 -07:00
Alex Forencich
202fbcbb6f Fix typo 2018-08-09 11:23:27 -07:00
Alex Forencich
2e9602b5b4 Update testbenches to use wait 2018-07-02 18:20:07 -07:00
Alex Forencich
65c64588a6 More endpoint updates 2018-07-02 16:33:13 -07:00
Alex Forencich
7775e7774d merged changes in axis 2018-07-02 16:26:21 -07:00
Alex Forencich
ffc63e4b0d Update readme 2018-07-02 16:25:29 -07:00
Alex Forencich
3063bba54b Update testbenches to use wait 2018-07-02 16:19:35 -07:00
Alex Forencich
9390c3639b More endpoint updates 2018-07-02 14:13:47 -07:00
Alex Forencich
63f9bbeced Update endpoints 2018-07-02 13:20:49 -07:00
Alex Forencich
4cb51ac84e merged changes in axis 2018-07-02 10:25:51 -07:00
Alex Forencich
268d011b89 Add wait method to sink 2018-06-30 00:21:26 -07:00
Alex Forencich
2ebffeb223 Be more pythonic 2018-06-30 00:21:02 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
5b7646ccda Rework ARP subsystem 2018-06-18 13:59:58 -07:00
Alex Forencich
25d1b373cc Use don't care bits 2018-06-14 15:20:20 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
20486d438a merged changes in axis 2018-06-13 22:36:26 -07:00
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00