FPGA/verilog-ethernet
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755 Commits 1 Branch 0 Tags
Commit Graph

22 Commits

Author SHA1 Message Date
Alex Forencich
b7c089dd22 XDC clean up 2020-07-13 23:58:30 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands 2019-06-26 20:06:22 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00
Alex Forencich
6d52a7c0e7 Remove unneeded links 2019-01-08 17:31:49 -08:00
Alex Forencich
2628249059 Add ADM-PCIE-9V3 example design 2019-01-08 17:27:21 -08:00