FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
755 Commits 1 Branch 0 Tags
Commit Graph

8 Commits

Author SHA1 Message Date
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00
Alex Forencich
2628249059 Add ADM-PCIE-9V3 example design 2019-01-08 17:27:21 -08:00