FPGA/verilog-ethernet
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165 Commits

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Author SHA1 Message Date
Alex Forencich
b892fd1172 Add UDP complete module and testbench 2015-02-26 22:57:24 -08:00
Alex Forencich
635f05e9c6 Remove udp_ip_protocol input 2015-02-26 22:37:40 -08:00
Alex Forencich
27f319b91e Fix UDP EP parse_eth 2015-02-26 22:36:05 -08:00
Alex Forencich
10108d5d1a Add 2 port IP mux components 2015-02-26 22:05:07 -08:00
Alex Forencich
b2ea1c8568 Add parameters to ip_complete testbenches 2015-02-26 21:41:51 -08:00
Alex Forencich
d34aaf784d Add UDP modules 2015-02-26 21:19:26 -08:00
Alex Forencich
ca94f1ded9 Update readme 2015-02-26 19:17:34 -08:00
Alex Forencich
b10beab08f Update readme 2015-02-26 19:16:17 -08:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00
Alex Forencich
bb31d57921 Add GMII endpoint module 2015-02-26 19:15:31 -08:00
Alex Forencich
218d3f1b0f Add assert for error_bad_fcs signal 2015-02-26 19:05:56 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00
Alex Forencich
bf847ff540 Update readme 2015-02-26 16:14:09 -08:00
Alex Forencich
da04654196 Add Ethernet FCS calculator modules 2015-02-26 16:11:04 -08:00
Alex Forencich
43fe36087c Update readme 2015-02-26 16:04:57 -08:00
Alex Forencich
9265ab0946 Properly handle eth_fcs of None 2015-02-26 15:58:20 -08:00
Alex Forencich
c25c35d198 Add Ethernet CRC modules 2015-02-25 14:40:26 -08:00
Alex Forencich
f3ea7cd8ac Add FCS field to eth_ep 2015-02-24 20:26:24 -08:00
Alex Forencich
7775733120 merged changes in axis 2014-12-03 21:48:34 -08:00
Alex Forencich
8582ab0749 Update readme 2014-12-03 19:00:12 -08:00
Alex Forencich
3c7e3b0424 Add SRL register module and testbench 2014-12-03 18:51:46 -08:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00
Alex Forencich
385e358c08 Use non-broken myhdl 2014-12-03 18:02:53 -08:00
Alex Forencich
a545ed5170 merged changes in axis 2014-12-03 13:55:08 -08:00
Alex Forencich
b83dd34185 Fix register names 2014-12-03 13:15:13 -08:00
Alex Forencich
51a3f77283 merged changes in axis 2014-11-21 10:43:52 -08:00
Alex Forencich
fbcbbe3a69 Remove adder tree 2014-11-21 10:43:20 -08:00
Alex Forencich
684c0b9c8a merged changes in axis 2014-11-21 01:07:43 -08:00
Alex Forencich
63f6e96492 Add tuser signal to crosspoint module 2014-11-21 01:07:02 -08:00
Alex Forencich
27cb9609f1 clog2 does not work in localparam in XST 2014-11-21 01:06:24 -08:00
Alex Forencich
d60844a399 Update readme 2014-11-21 00:20:54 -08:00
Alex Forencich
32a66ed014 Update readme 2014-11-21 00:15:30 -08:00
Alex Forencich
4a228f06c5 Add IP complete module and testbench 2014-11-21 00:03:08 -08:00
Alex Forencich
9bf6f01649 Add 2 port Ethernet mux components 2014-11-21 00:02:20 -08:00
Alex Forencich
96b6e7ca96 Ignore transient requests 2014-11-21 00:00:27 -08:00
Alex Forencich
d483ebb8da Drop arp request earlier 2014-11-20 23:59:54 -08:00
Alex Forencich
a8bb020839 Reorder includes 2014-11-20 23:51:24 -08:00
Alex Forencich
2ae3581144 Add ARP module and testbench 2014-11-20 22:55:28 -08:00
Alex Forencich
7fdb7b4f35 Add ARP cache module 2014-11-20 22:54:08 -08:00
Alex Forencich
f35ecece83 Initialize tkeep properly 2014-11-20 22:52:52 -08:00
Alex Forencich
fc6ccd97fb Rework IP modules 2014-11-20 12:11:11 -08:00
Alex Forencich
d1b6e69079 merged changes in axis 2014-11-20 00:22:30 -08:00
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
3dfcac97ce Update readme 2014-11-19 17:07:01 -08:00
Alex Forencich
495bb2714f Update readme 2014-11-19 16:21:02 -08:00
Alex Forencich
64f6488bf1 Add UDP demux module and testbench 2014-11-18 15:17:50 -08:00
Alex Forencich
1b69fc5eed Add UDP arbitrated mux and testbench 2014-11-18 14:53:31 -08:00
Alex Forencich
a5d68fcff9 Add UDP mux module and testbench 2014-11-18 14:41:48 -08:00
Alex Forencich
348a347616 Add IP demux and testbench 2014-11-18 12:36:12 -08:00
Alex Forencich
fbca60e65e Add IP arbitrated mux and testbench 2014-11-18 11:48:11 -08:00