Alex Forencich
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baac5f8d81
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Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2024-02-12 17:29:31 -08:00 |
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Alex Forencich
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870cebb798
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Clean up PTP parameters on MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2024-02-11 13:00:37 -08:00 |
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Alex Forencich
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fa05d4ff3c
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Add TX and RX enable inputs to MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-24 01:24:33 -07:00 |
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Alex Forencich
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20c542051d
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Use cfg prefix for configuration signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-22 17:14:52 -07:00 |
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Alex Forencich
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2858aaaef7
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Add TX PTP timestamp enable bit in tuser
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-17 10:58:40 -07:00 |
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Alex Forencich
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1f0b6a625c
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PTP parameter clean-up
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-06 16:46:32 -07:00 |
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Alex Forencich
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77adf30dad
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Add missing serdes_rx_reset_req output to 10G MAC+PHY modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-22 17:36:01 -08:00 |
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Alex Forencich
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85e4f1d8ba
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Add PHY RX status output for a more reliable link up indication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-16 23:22:30 -07:00 |
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Alex Forencich
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6b18e56cb1
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Add default_nettype none and resetall directives
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2021-10-20 17:29:12 -07:00 |
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Alex Forencich
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5e1329a992
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Rework PHY bitslip timing
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2021-05-05 00:35:43 -07:00 |
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Alex Forencich
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e9949f57a9
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Remove extraneous code
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2019-08-05 13:27:12 -07:00 |
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Alex Forencich
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134ce04777
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Add configurable serdes pipeline register chain
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2019-06-19 00:57:28 -07:00 |
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Alex Forencich
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6eff2f0030
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Decouple transmit PTP tag enable and transmit PTP timestamp enable
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2019-06-09 22:03:24 -07:00 |
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Alex Forencich
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82fe5a6bdd
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Add PTP timestamp capture logic to MACs
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2019-06-07 16:38:36 -07:00 |
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Alex Forencich
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659aa67481
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Pack start packet strobes into the same signal
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2019-06-06 17:13:14 -07:00 |
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Alex Forencich
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79ec137243
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Add PRBS31 generation and checking to 10G PHY
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2019-05-10 20:28:45 -07:00 |
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Alex Forencich
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696c634726
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Add rx_bad_block outputs
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2019-04-17 00:16:45 -07:00 |
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Alex Forencich
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585ccefa15
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Add TX underflow error signal
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2019-03-26 12:42:08 -07:00 |
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Alex Forencich
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ec38440d89
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Add 10G Ethernet MAC/PHY combination modules and testbenches
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2019-01-31 18:13:07 -08:00 |
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