FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
c5d069444a Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:03 -08:00
Alex Forencich
dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-02 00:53:02 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00