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Author SHA1 Message Date
Alex Forencich
98b15b6226 merged changes in axis 2015-10-09 15:21:26 -07:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00
Alex Forencich
382226ad59 Don't accept data until reset is complete 2015-10-08 23:46:59 -07:00
Alex Forencich
90ac361df5 Internal synchronous reset on async FIFOs 2015-10-08 13:03:42 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
4156d8511a Rework CRC check 2015-08-07 12:13:44 -07:00
Alex Forencich
af8bed8237 Update for compatibility with older versions of Python 2015-07-14 08:29:54 -07:00
Alex Forencich
cf34be5b7c merged changes in axis 2015-07-14 08:29:17 -07:00
Alex Forencich
26b165227c Update for compatibility with older versions of Python 2015-07-14 08:27:49 -07:00
Alex Forencich
120f86f4cf Add SRL FIFO reset tests 2015-07-13 23:15:39 -07:00
Alex Forencich
ac97cffc2b Properly reset all registers 2015-07-13 23:15:09 -07:00
Alex Forencich
dfab866e99 Remove unused reg 2015-07-13 23:09:02 -07:00
Alex Forencich
88f3e97bad Update readme 2015-07-09 11:52:06 -07:00
Alex Forencich
2667c9c631 Update for compatibility with older version of Python 2015-07-09 11:35:55 -07:00
Alex Forencich
5d4ba0fdfb merged changes in axis 2015-07-09 11:35:39 -07:00
Alex Forencich
04e4ccc517 Update for compatibility with older version of Python 2015-07-09 11:25:49 -07:00
Alex Forencich
516c50d786 Add FIFO reset tests 2015-07-09 11:13:25 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
6bd7309b9d Properly reset all registers 2015-07-09 11:11:32 -07:00
Alex Forencich
abe0d926ba Consider any control characters in packet body as errors 2015-06-23 08:55:39 -07:00
Alex Forencich
dbf720ffbe Improve 10G PHY TX timing performance 2015-06-23 07:43:06 -07:00
Alex Forencich
8821ae0593 merged changes in axis 2015-06-22 14:59:15 -07:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00
Alex Forencich
0ecd354d7f Fix instance name 2015-06-07 22:07:04 -07:00
Alex Forencich
455ddf5df2 Fix error detect in 10G MAC 2015-06-06 00:49:40 -07:00
Alex Forencich
bfc97ac311 Fix error detect in 1G MAC 2015-06-05 23:42:43 -07:00
Alex Forencich
13afff6686 merged changes in axis 2015-06-05 17:46:11 -07:00
Alex Forencich
c15761068a Add AXI stream frame length adjust modules 2015-06-05 17:04:10 -07:00
Alex Forencich
14a2caa994 Rework 10G ethernet MAC TX to add input register 2015-05-17 01:39:59 -07:00
Alex Forencich
0352d55084 Add default case 2015-05-16 22:34:29 -07:00
Alex Forencich
15edfa0f85 Add missing initialize 2015-05-16 22:32:02 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
22124ec361 merged changes in axis 2015-05-12 17:58:45 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
e72b93033d Add parameters to axis_stat_counter testbench 2015-05-12 17:54:37 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
8fea20ef77 Fix frame_ptr_reg width 2015-05-12 16:57:14 -07:00
Alex Forencich
8b762a6009 Add asserts to check for orphaned payloads 2015-05-08 21:25:37 -07:00
Alex Forencich
8aa5ec5118 Improve ip_eth_rx_64 module timing performance 2015-05-08 21:06:33 -07:00
Alex Forencich
5ae8eb9611 Improve ip_eth_tx_64 module timing performance 2015-05-08 20:37:31 -07:00
Alex Forencich
c9c0bda56f merged changes in axis 2015-05-08 01:46:23 -07:00
Alex Forencich
6b23d83361 Set FIFO size in example design 2015-05-08 01:45:42 -07:00
Alex Forencich
16fec34ddc Default FIFO size at least 2 MTU (3000 bytes) 2015-05-08 01:44:55 -07:00
Alex Forencich
51e65f5a22 Rework async FIFO resets and synchronization 2015-05-08 01:41:35 -07:00
Alex Forencich
6a012c992b Update example design to use FIFO wrapper 2015-05-08 00:45:27 -07:00
Alex Forencich
bf0571332d Update readme 2015-05-08 00:12:09 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00
Alex Forencich
bf349b16ba Add 10G MAC module 2015-05-08 00:05:21 -07:00
Alex Forencich
17edcfe88e Add XGMII endpoint module 2015-05-08 00:04:12 -07:00