FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
410 Commits 1 Branch 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
9fdc36450a Update NexysVideo reference design 2017-05-31 19:44:39 -07:00
Alex Forencich
0fc986041e Fix example design LED logic 2017-05-19 17:44:29 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
15330486e8 Convert GMII and RGMII shims to use generic IO components 2016-09-29 20:10:10 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
1f52bf826d Update vivado.mk 2016-07-05 11:17:16 -04:00
Alex Forencich
cbf1df718a Add example design for Digilent Nexys Video board 2016-06-29 12:00:05 -07:00