Alex Forencich
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bd8e8e5b20
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Add PTP time distribution components
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-07 13:07:15 -08:00 |
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Alex Forencich
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90e6dfc638
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Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-23 14:58:44 -07:00 |
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Alex Forencich
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5a37442706
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Merge FNS registers into NS registers in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-22 22:52:59 -07:00 |
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Alex Forencich
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cf441f004d
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Rename source sync signals in PTP CDC module for consistency
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-22 01:07:12 -07:00 |
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Alex Forencich
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a443e8862c
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Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-26 14:59:19 -07:00 |
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Alex Forencich
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70cc19ff15
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Add MAC control layer to core 1G and 10G MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-23 22:24:42 -07:00 |
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Alex Forencich
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274831c268
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Fix PTP clock CDC module timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-05 21:41:41 -07:00 |
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Alex Forencich
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7751aba8da
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Reorganize timing constraints
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2021-05-18 16:15:41 -07:00 |
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