FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
104 Commits 1 Branch 0 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
7a9fdb5fc3 Add default case statements to avoid inferring latches 2015-11-09 14:54:14 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
7c86999399 Minor reorganization 2014-11-13 16:26:07 -08:00
Alex Forencich
5af6dc3501 Add AXI stream mux and testbench 2014-11-12 15:49:07 -08:00