FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00