FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
243 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Alex Forencich
bfc97ac311 Fix error detect in 1G MAC 2015-06-05 23:42:43 -07:00
Alex Forencich
3a180bd24f Improve error signal handling 2015-05-07 19:08:16 -07:00
Alex Forencich
71511b3671 Remove unused register 2015-04-20 23:37:57 -07:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00