FPGA/verilog-ethernet
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714 Commits 1 Branch 0 Tags
Commit Graph

164 Commits

Author SHA1 Message Date
Alex Forencich
bfef06ca0e Separate UDP pseudo header checksum computation 2019-07-29 18:53:32 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
4e49dbcf3d Pass parameters to model 2019-07-18 22:51:54 -07:00
Alex Forencich
8cb0a5e06e Add parameters for PTP clock model 2019-07-18 22:49:29 -07:00
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
021c91fcc7 Unconditionally wait at least one delta cycle 2019-07-16 00:37:20 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
3ba91ce091 Wait for block lock 2019-06-19 00:53:41 -07:00
Alex Forencich
d96a5a449a Update ARP cache testbench 2019-06-14 00:01:51 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
2efcfdb0a0 Add PTP clock simulation model 2019-06-03 19:08:16 -07:00
Alex Forencich
e181ea5abc Add PTP clock module and testbench 2019-06-03 19:00:28 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
e34c72da1f Add missing parameter 2019-05-10 17:23:55 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
013e88253e Testbench updates 2019-03-07 23:44:43 -08:00
Alex Forencich
c1fe89db62 Add bit reverse support to serdes endpoint 2019-01-31 18:14:06 -08:00
Alex Forencich
ec38440d89 Add 10G Ethernet MAC/PHY combination modules and testbenches 2019-01-31 18:13:07 -08:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
a743f6f789 Add zero IFG forced offset start test 2019-01-22 18:47:32 -08:00
Alex Forencich
5b2d4fd465 Add force offset start parameter 2019-01-22 18:46:34 -08:00
Alex Forencich
4d2090a1a5 Fix off-by-one error in control character checks 2019-01-22 14:24:35 -08:00
Alex Forencich
92df3778ea Fix DIC implementation in testbench 2019-01-22 14:23:29 -08:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00
Alex Forencich
91553e6edf Add XGMII 10GBASE-R encoder and decoder modules and testbenches 2019-01-16 17:30:07 -08:00
Alex Forencich
c9752f24dd Add BASE-R SERDES endpoint model 2019-01-16 17:26:19 -08:00
Alex Forencich
5fbd67501c Clamp ifg_cnt at zero 2019-01-16 17:25:08 -08:00
Alex Forencich
128dc292a1 Add short IFG tests 2019-01-16 13:27:28 -08:00
Alex Forencich
bf94ef56b8 Move ifg parameter 2019-01-16 13:23:02 -08:00
Alex Forencich
fe8a4f9df3 Use constants for control characters 2018-11-11 00:18:32 -08:00
Alex Forencich
6a4b2699ea End frame reception on any control character 2018-11-11 00:11:27 -08:00
Alex Forencich
25e196e18b Insert idle characters 2018-11-10 18:56:50 -08:00
Alex Forencich
b195c6450b Add IFG parameter 2018-11-10 18:23:44 -08:00
Alex Forencich
a49b78b3c3 Add width asserts 2018-11-10 18:23:31 -08:00
Alex Forencich
b6c8cc7125 Append termination control character 2018-11-10 18:16:30 -08:00
Alex Forencich
0159376cda Simplify IFG count handling 2018-11-10 17:35:31 -08:00
Alex Forencich
d59a0553bd Change start character handling 2018-11-09 16:51:54 -08:00
Alex Forencich
261ad46a8a Add enable signals to xgmii model 2018-11-09 16:47:19 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
b3f50ac2c7 Fix comments 2018-11-02 00:40:15 -07:00
Alex Forencich
98fc042489 Convert generated udp_demux to verilog parametrized module 2018-11-02 00:39:52 -07:00
Alex Forencich
81e9aa0c77 Convert generated ip_demux to verilog parametrized module 2018-11-02 00:25:23 -07:00