FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
00d69a341c Test with sample clock on and off 2021-03-27 14:44:36 -07:00
Alex Forencich
55359c1755 Report difference in ns 2021-03-27 14:44:21 -07:00
Alex Forencich
3cbe4b04da Improve timestamp difference measurement 2021-03-27 14:38:35 -07:00
Alex Forencich
8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc 2020-12-29 22:55:55 -08:00