FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
233 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00