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Author SHA1 Message Date
Alex Forencich
731fd859ac Add Github Actions regression tests 2020-12-28 20:19:58 -08:00
Alex Forencich
4a98858bea Forward arguments to pytest 2020-12-28 20:19:46 -08:00
Alex Forencich
f47c529122 Add test durations 2020-12-28 19:33:56 -08:00
Alex Forencich
cd12721502 Add cococb testbenches for eth_axis_rx and eth_axis_tx 2020-12-28 19:28:38 -08:00
Alex Forencich
29dc7498d3 Add cocotb MAC testbenches 2020-12-28 19:26:46 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
a894af4815 Add tox.ini 2020-12-28 01:12:08 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
4d31316fef Remove travis-ci 2020-12-25 02:09:50 -08:00
Alex Forencich
d1fc821c8b Fix simulation startup issue in rgmii_phy_if 2020-12-25 02:03:57 -08:00
Alex Forencich
a78627343d Change default target parameter 2020-12-25 01:48:24 -08:00
Alex Forencich
220e04d1a7 Update example design 2020-12-25 01:47:01 -08:00
Alex Forencich
2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs 2020-12-20 14:22:52 -08:00
Alex Forencich
d834e49587 Move wire declarations 2020-12-03 17:37:53 -08:00
Alex Forencich
1f9aa62639 Add wrapper generator for axis_broadcast 2020-12-03 17:31:11 -08:00
Alex Forencich
909ccae151 Properly synchronize bad FCS status output 2020-12-01 14:01:15 -08:00
Alex Forencich
306aa4db0b Update VCU118 XDC 2020-10-06 00:39:32 -07:00
Alex Forencich
ed7136a095 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:27:30 -07:00
Alex Forencich
9261f26f64 Update VCU108 XDC 2020-10-02 20:50:00 -07:00
Alex Forencich
9e4bd6e854 Fix flash programming commands for VCU108 2020-10-01 00:53:13 -07:00
Alex Forencich
816e071a57 Fix bitstream config for VCU1525 2020-09-30 23:50:31 -07:00
Alex Forencich
bf9f1a6211 Update flash programming commands 2020-09-29 18:29:27 -07:00
Alex Forencich
3f52ed675c Fix flash settings 2020-09-29 17:30:13 -07:00
Alex Forencich
2bc052e0d5 Update LED driver timing constraints 2020-09-28 17:24:11 -07:00
Alex Forencich
d0a45d8213 Add fb2CG flash programming commands 2020-09-27 01:45:56 -07:00
Alex Forencich
82cf0d5a6f Use correct init_clk frequency 2020-09-23 14:24:18 -07:00
Alex Forencich
99b06b0ed2 Update readme 2020-09-22 23:04:44 -07:00
Alex Forencich
6a4bcaab38 Add timing constraints for LED driver 2020-09-22 22:13:59 -07:00
Alex Forencich
a7972e32bb Add fb2CG 10G example design 2020-09-20 01:18:47 -07:00
Alex Forencich
c9d8b8508e Update readme 2020-09-18 01:26:17 -07:00
Alex Forencich
4db7f50ad8 Update readme 2020-09-18 01:26:09 -07:00
Alex Forencich
c9a023c1e0 Add AU250 10G example design 2020-09-18 01:20:42 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00
Alex Forencich
b65bc94b4c Update readme 2020-09-18 00:16:25 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00
Alex Forencich
6df648ef54 merged changes in axis 2020-09-07 18:55:12 -07:00
Alex Forencich
da152a8546 Update timing parameters for async FIFO to reflect new pipeline register naming 2020-09-07 18:54:32 -07:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
dff38e2c1d Add UDP test script 2020-09-07 16:32:00 -07:00
Alex Forencich
ad47169480 Add netns shell script 2020-09-07 16:28:18 -07:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
59a9585253 merged changes in axis 2020-09-07 00:42:44 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
4b5cdce7ab merged changes in axis 2020-09-03 15:56:55 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00