FPGA/verilog-ethernet
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7 Commits

Author SHA1 Message Date
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
d483ebb8da Drop arp request earlier 2014-11-20 23:59:54 -08:00
Alex Forencich
fc6ccd97fb Rework IP modules 2014-11-20 12:11:11 -08:00
Alex Forencich
e14a79dee4 Add IP module and testbench 2014-09-29 22:26:55 -07:00