FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
33c044e035 Add invalid header and tuser assert checks and tests 2014-09-15 19:31:10 -07:00
Alex Forencich
85d11645eb Rename frame_error to error_header_early_termination 2014-09-15 19:08:01 -07:00
Alex Forencich
ea2b1b99d0 Add ARP frame to Ethernet frame modules 2014-09-15 19:06:02 -07:00