FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
f11f7ecac9 Rework GT instances in Alveo U200 design 2021-10-19 17:45:43 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
bf9f1a6211 Update flash programming commands 2020-09-29 18:29:27 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00