FPGA/verilog-ethernet
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16 Commits

Author SHA1 Message Date
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:59:33 -07:00
Alex Forencich
4ce218bc5d Rework GT instances in ADM-PCIE-9V3 designs 2021-10-19 18:29:18 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands 2019-06-26 20:06:22 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00