FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
1,200 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
be0d9b7b88 Improve handling of instance name mangling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 13:37:25 -08:00
Alex Forencich
a443e8862c Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:59:19 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00