FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
274831c268 Fix PTP clock CDC module timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 21:41:41 -07:00
Alex Forencich
40265a3e1c Add timing constraints for Quartus Prime Pro 2021-05-18 18:30:33 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
59a51b4a9f Add SDC constraints for Quartus 2020-07-10 14:14:02 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
58201866f3 Add timing constraints 2019-03-28 17:53:51 -07:00