FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
2bf15706cd Convert generated mux to verilog parametrized mux 2018-10-24 18:23:14 -07:00