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Author SHA1 Message Date
Alex Forencich
d0ef5f94a4 merge changes in axis 2018-02-27 01:46:35 -08:00
Alex Forencich
7c6da337b0 Happy new year 2018-02-27 01:39:25 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
0807a54c32 merged changes in axis 2018-02-26 12:45:29 -08:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
3063a761e5 Support both versions of ML605 2018-02-26 00:18:14 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
18787c2eed merged changes in axis 2017-12-01 00:02:34 -08:00
Alex Forencich
c33985d7ba Remove extraneous parameter 2017-11-21 08:54:21 -08:00
Alex Forencich
93688dc88e Update readme 2017-11-21 00:21:15 -08:00
Alex Forencich
4ec4c901e8 Whitespace fixes 2017-11-21 00:18:09 -08:00
Alex Forencich
b00eaf4d3c Add tkeep signal and update testbench for stat counter 2017-11-21 00:17:42 -08:00
Alex Forencich
ad0e3e1eb5 Whitespace fixes and testbench update for frame joiner 2017-11-21 00:16:15 -08:00
Alex Forencich
a1a6d523e3 Update FIFO instances and testbenches for COBS encoder and decoder 2017-11-21 00:14:26 -08:00
Alex Forencich
0edafd58ac Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap 2017-11-20 23:45:34 -08:00
Alex Forencich
4ef4ef2622 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register 2017-11-20 21:34:25 -08:00
Alex Forencich
b0d7820f5b Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO 2017-11-20 21:32:46 -08:00
Alex Forencich
d16f19f67e Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter 2017-11-20 21:31:41 -08:00
Alex Forencich
772e433ee9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster 2017-11-20 21:30:26 -08:00
Alex Forencich
de590517a9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch 2017-11-20 20:17:20 -08:00
Alex Forencich
91a7169f46 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint 2017-11-20 20:16:21 -08:00
Alex Forencich
496c63bd1c Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux 2017-11-20 20:15:08 -08:00
Alex Forencich
57e700f802 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux 2017-11-20 20:14:20 -08:00
Alex Forencich
9e4aa38750 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux 2017-11-20 20:13:53 -08:00
Alex Forencich
d50c767482 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter 2017-11-20 20:12:43 -08:00
Alex Forencich
fdb881719c Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO 2017-11-20 20:12:02 -08:00
Alex Forencich
1c7362c717 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO 2017-11-20 20:11:44 -08:00
Alex Forencich
7d237f55c1 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO 2017-11-20 20:11:08 -08:00
Alex Forencich
190d75df9d Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO 2017-11-20 20:10:41 -08:00
Alex Forencich
a5524287ca Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register 2017-11-20 20:09:48 -08:00
Alex Forencich
a0b21db746 Improve checks in axis_ep 2017-11-20 15:43:54 -08:00
Alex Forencich
c9cc9006a3 Add last_cycle_user parameter to axis_ep 2017-11-20 15:43:32 -08:00
Alex Forencich
cb2221b39b Use correct path 2017-11-12 18:36:15 -08:00
Alex Forencich
a51109c7c4 Use latest python 2017-11-12 18:30:08 -08:00
Alex Forencich
a35d1a8e7c Fix CI 2017-11-12 18:22:41 -08:00
Alex Forencich
7dc58e5d49 Add tid signal to axis_ep 2017-11-12 18:17:33 -08:00
Alex Forencich
cf6a01fffe Add ML605 SGMII design 2017-07-22 11:07:23 -07:00
Alex Forencich
eb47bea9a1 Use correct clock in testbench 2017-06-09 21:28:08 -07:00
Alex Forencich
77211926f2 Fix classifier logic 2017-06-09 21:27:29 -07:00
Alex Forencich
9a507b388d Update LFSR module 2017-06-09 21:17:28 -07:00
Alex Forencich
69253d2d83 Update VCU108 example design 2017-06-01 06:48:50 -07:00
Alex Forencich
1b6816b06f Add ML605 RGMII example design 2017-05-31 20:24:43 -07:00
Alex Forencich
de00b3e233 Rename ML605 example design 2017-05-31 20:06:32 -07:00
Alex Forencich
e376c805d2 Update ML605 reference design 2017-05-31 19:52:43 -07:00
Alex Forencich
9fdc36450a Update NexysVideo reference design 2017-05-31 19:44:39 -07:00
Alex Forencich
a8a423da0e Update Atlys example design 2017-05-31 19:35:40 -07:00
Alex Forencich
a3b5d5d167 Update RGMII PHY interface and add RGMII MAC wrappers 2017-05-31 18:40:49 -07:00
Alex Forencich
bb9e789645 Update GMII PHY interface and add GMII MAC wrappers 2017-05-31 18:40:18 -07:00
Alex Forencich
8ff4312601 Update MAC modules to use new modules 2017-05-31 18:37:33 -07:00
Alex Forencich
817e7c2667 Add AXI stream GMII RX and TX modules and testbenches 2017-05-31 16:11:20 -07:00