FPGA/verilog-ethernet
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516 Commits 1 Branch 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
0aca4c7dcc Update 10G MAC to use new modules 2018-10-24 00:54:41 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
bf349b16ba Add 10G MAC module 2015-05-08 00:05:21 -07:00