FPGA/verilog-ethernet
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160 Commits 1 Branch 0 Tags
Commit Graph

52 Commits

Author SHA1 Message Date
Alex Forencich
d34aaf784d Add UDP modules 2015-02-26 21:19:26 -08:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00
Alex Forencich
bb31d57921 Add GMII endpoint module 2015-02-26 19:15:31 -08:00
Alex Forencich
218d3f1b0f Add assert for error_bad_fcs signal 2015-02-26 19:05:56 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00
Alex Forencich
da04654196 Add Ethernet FCS calculator modules 2015-02-26 16:11:04 -08:00
Alex Forencich
9265ab0946 Properly handle eth_fcs of None 2015-02-26 15:58:20 -08:00
Alex Forencich
f3ea7cd8ac Add FCS field to eth_ep 2015-02-24 20:26:24 -08:00
Alex Forencich
4a228f06c5 Add IP complete module and testbench 2014-11-21 00:03:08 -08:00
Alex Forencich
a8bb020839 Reorder includes 2014-11-20 23:51:24 -08:00
Alex Forencich
2ae3581144 Add ARP module and testbench 2014-11-20 22:55:28 -08:00
Alex Forencich
7fdb7b4f35 Add ARP cache module 2014-11-20 22:54:08 -08:00
Alex Forencich
64f6488bf1 Add UDP demux module and testbench 2014-11-18 15:17:50 -08:00
Alex Forencich
1b69fc5eed Add UDP arbitrated mux and testbench 2014-11-18 14:53:31 -08:00
Alex Forencich
a5d68fcff9 Add UDP mux module and testbench 2014-11-18 14:41:48 -08:00
Alex Forencich
348a347616 Add IP demux and testbench 2014-11-18 12:36:12 -08:00
Alex Forencich
fbca60e65e Add IP arbitrated mux and testbench 2014-11-18 11:48:11 -08:00
Alex Forencich
f6fcec08f3 Add IP mux module and testbench 2014-11-18 11:27:34 -08:00
Alex Forencich
4db581ae3c Add ethernet demux module and testbench 2014-11-17 21:52:49 -08:00
Alex Forencich
4d1180d74c Reverse priority in arbitrated mux 2014-11-16 02:20:44 -08:00
Alex Forencich
f1d075d974 Add enable signal 2014-11-16 02:13:43 -08:00
Alex Forencich
c90d5141ac Add ethernet arbitrated mux module and testbench 2014-11-14 22:11:49 -08:00
Alex Forencich
9bee01e74c Add ethernet mux and testbench 2014-11-14 17:48:51 -08:00
Alex Forencich
96c6fcd144 Remove AXI stream components 2014-11-05 16:59:59 -08:00
Alex Forencich
7e01c6c14c Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
63843e9d5d Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
09d0d87939 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
8e9b38cde0 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
8bce338bc0 Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
2495dd2bac Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00
Alex Forencich
e14a79dee4 Add IP module and testbench 2014-09-29 22:26:55 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00
Alex Forencich
20da100db6 Add UDP transmit and receive modules 2014-09-25 16:52:42 -07:00
Alex Forencich
0f1eb94148 Calculate header checksum for truncated packets 2014-09-25 16:26:59 -07:00
Alex Forencich
ebc1c7ccc6 Rename checksum to calc_checksum in ip_ep 2014-09-25 16:26:23 -07:00
Alex Forencich
c6236bc647 Add 64-bit datapath version of IP modules 2014-09-25 00:40:48 -07:00
Alex Forencich
3bee612dfd Add extra delays to IP testbenches 2014-09-25 00:39:22 -07:00
Alex Forencich
33a61d8d89 Rework Ethernet module testbenches 2014-09-25 00:36:08 -07:00
Alex Forencich
3fdd453e0f Rework IP module testbenches 2014-09-21 15:56:12 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00
Alex Forencich
4ad302949f Add defaults 2014-09-19 17:33:23 -07:00
Alex Forencich
fa72cc2035 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
fdb31878e9 Remove length fields from ARP transmit module 2014-09-17 12:36:56 -07:00
Alex Forencich
33c044e035 Add invalid header and tuser assert checks and tests 2014-09-15 19:31:10 -07:00
Alex Forencich
85d11645eb Rename frame_error to error_header_early_termination 2014-09-15 19:08:01 -07:00
Alex Forencich
ea2b1b99d0 Add ARP frame to Ethernet frame modules 2014-09-15 19:06:02 -07:00
Alex Forencich
96f1e432f4 Remove old code 2014-09-15 19:02:41 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00
Alex Forencich
e1955a29da Add LocalLink to AXI stream bridge 2014-09-13 21:23:11 -07:00