FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
176 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Forencich
d57c857d88 Put PHY interface registers into IOBs for timing 2015-02-28 18:24:20 -08:00
Alex Forencich
7532915bb7 Add GMII PHY interface module 2015-02-28 01:11:03 -08:00