FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
0ecd354d7f Fix instance name 2015-06-07 22:07:04 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00