FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:20 -07:00