FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
57e700f802 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux 2017-11-20 20:14:20 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
5c49ed6191 Add AXI stream demux and testbench 2014-11-12 19:21:28 -08:00