FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
960a2eab61 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:56:40 -08:00
Alex Forencich
b81e323a6d Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 20:53:11 -08:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
74c1014671 Add cocotb testbenches 2021-04-03 16:53:08 -07:00