FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
e34c72da1f Add missing parameter 2019-05-10 17:23:55 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00