FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
b38c643384 Add more implementation parameters to gmii_phy_if 2016-06-28 19:35:52 -07:00
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
c5b6202174 Update example design 2016-01-08 01:32:04 -08:00
Alex Forencich
6b23d83361 Set FIFO size in example design 2015-05-08 01:45:42 -07:00
Alex Forencich
6a012c992b Update example design to use FIFO wrapper 2015-05-08 00:45:27 -07:00
Alex Forencich
5341987c45 Manage ethernet preamble properly 2015-04-01 19:44:25 -07:00
Alex Forencich
92830f87d8 Update for Python 3 2015-04-01 19:43:54 -07:00
Alex Forencich
d489468776 Add example design for Digilent Atlys board 2015-02-28 20:05:05 -08:00