FPGA/verilog-ethernet
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Author SHA1 Message Date
Alex Forencich
e3fcb0fa1d Test shorter frames 2019-04-26 18:36:09 -07:00
Alex Forencich
a9c7946368 Change parameter concatenation to increments of DEST_WIDTH 2019-03-28 23:49:04 -07:00
Alex Forencich
ad3905ac4d Account for more merged registers 2019-03-28 16:33:01 -07:00
Alex Forencich
e938844783 Account for merged registers 2019-03-27 23:54:48 -07:00
Alex Forencich
48984013de Add AXI stream async FIFO timing constraints 2019-03-26 18:46:25 -07:00
Alex Forencich
932aa35451 Fix AXI stream async frame FIFO write pointer synchronization 2019-03-26 18:45:54 -07:00
Alex Forencich
3920b2801e Add short packet tests 2019-03-26 16:39:31 -07:00
Alex Forencich
88badf13f0 Reset all status synchronization stages 2019-03-26 16:19:49 -07:00
Alex Forencich
414f091c2c Properly handle width of 1 2019-03-07 22:59:49 -08:00
Alex Forencich
b1f3a74b86 Remove unused code 2019-03-07 22:59:15 -08:00
Alex Forencich
d2df971fc9 Add AXI stream frame length measurement module and testbenches 2019-03-07 22:57:46 -08:00
Alex Forencich
e0f740457b Testbench updates 2019-03-07 22:51:40 -08:00
Alex Forencich
b60886a0ec Add AXI stream broadcast module and testbench 2019-02-27 19:46:30 -08:00
Alex Forencich
59a979aeda Add parameters to testbench 2018-12-09 00:05:38 -08:00
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
f9a5e6803b Add backpressure tests 2018-12-08 23:59:57 -08:00
Alex Forencich
f45a3ef5e0 Change cycle to segment 2018-12-03 12:40:06 -08:00
Alex Forencich
a72d7bd260 Fix generate statement 2018-11-28 14:18:09 -08:00
Alex Forencich
8d564b1074 Convert localparam to parameter as Vivado does not like clog2 in localparams 2018-10-30 17:35:38 -07:00
Alex Forencich
be51f2b472 Update FIFO instantiations 2018-10-25 16:06:32 -07:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
ebe9d17bd5 Update readme 2018-10-25 14:30:42 -07:00
Alex Forencich
ed4a2d73c2 Add axis_pipeline_register module 2018-10-25 14:29:35 -07:00
Alex Forencich
ceedd0f8f5 Update readme 2018-10-25 14:27:24 -07:00
Alex Forencich
312d90addb Add wrapper generators 2018-10-25 14:23:00 -07:00
Alex Forencich
49d415d59f Disable dump file output under travis-ci 2018-10-25 12:14:12 -07:00
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
6f4ab8f180 Rename ports 2018-10-25 11:59:13 -07:00
Alex Forencich
84a758f100 Rename ports 2018-10-25 11:56:52 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
7997a4a844 Rename ports 2018-10-25 11:19:28 -07:00
Alex Forencich
8d9da455cd Minor optimizations 2018-10-25 10:29:31 -07:00
Alex Forencich
e926daabaf Update readme 2018-10-25 10:24:42 -07:00
Alex Forencich
cb9f2132a4 Update parameter ordering 2018-10-25 10:20:17 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00
Alex Forencich
c47f3ea03d Update FIFO instance, rename ports 2018-10-25 10:17:58 -07:00
Alex Forencich
d1ed1528b5 Update FIFO instance, rename ports 2018-10-25 10:15:16 -07:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports 2018-10-24 23:16:06 -07:00
Alex Forencich
3d2efef93a Update readme 2018-10-24 22:25:02 -07:00
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
3bbf8524d6 Compute DEST_WIDTH 2018-10-24 22:21:31 -07:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
145ea2c40c Connect arbiter parameters to top level 2018-10-24 21:09:00 -07:00
Alex Forencich
2bf15706cd Convert generated mux to verilog parametrized mux 2018-10-24 18:23:14 -07:00
Alex Forencich
029d1fa06f Fix loop count variable scoping issue 2018-10-24 17:58:39 -07:00