FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
431 Commits 1 Branch 0 Tags
Commit Graph

12 Commits

Author SHA1 Message Date
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
a8a423da0e Update Atlys example design 2017-05-31 19:35:40 -07:00
Alex Forencich
0fc986041e Fix example design LED logic 2017-05-19 17:44:29 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
b38c643384 Add more implementation parameters to gmii_phy_if 2016-06-28 19:35:52 -07:00
Alex Forencich
c5b6202174 Update example design 2016-01-08 01:32:04 -08:00
Alex Forencich
6b23d83361 Set FIFO size in example design 2015-05-08 01:45:42 -07:00
Alex Forencich
6a012c992b Update example design to use FIFO wrapper 2015-05-08 00:45:27 -07:00
Alex Forencich
d489468776 Add example design for Digilent Atlys board 2015-02-28 20:05:05 -08:00