FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
6238ed5755 Report error for invalid encoding 2019-01-22 14:19:43 -08:00
Alex Forencich
e784900050 Remove unused code 2019-01-22 14:18:27 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00