FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
9cca78bc7c Fix last cycle detect logic 2015-04-19 23:33:34 -07:00
Alex Forencich
7795a9182b Remove tristate for state machine inference 2015-04-19 23:08:41 -07:00
Alex Forencich
f827b5eafb Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00