FPGA/verilog-ethernet
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9 Commits

Author SHA1 Message Date
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
3063bba54b Update testbenches to use wait 2018-07-02 16:19:35 -07:00
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
0edafd58ac Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap 2017-11-20 23:45:34 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00