FPGA/verilog-ethernet
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7 Commits

Author SHA1 Message Date
Alex Forencich
fe77db822d Convert generated crosspoint to verilog parametrized crosspoint 2018-10-24 13:44:39 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
91a7169f46 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint 2017-11-20 20:16:21 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
a28a534bff Add AXI stream crosspoint module and testbench 2014-11-12 01:54:31 -08:00