FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
33a61d8d89 Rework Ethernet module testbenches 2014-09-25 00:36:08 -07:00
Alex Forencich
85d11645eb Rename frame_error to error_header_early_termination 2014-09-15 19:08:01 -07:00
Alex Forencich
96f1e432f4 Remove old code 2014-09-15 19:02:41 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00