FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
73bd619d85 Add NetFPGA SUME example design 2020-03-27 19:01:50 -07:00