FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
b34f294900 Add ExaNIC X25 10G example design 2019-10-30 17:14:27 -07:00