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Author SHA1 Message Date
Alex Forencich
f4a8561652 Add HTG-9200 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:59 -07:00
Alex Forencich
6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:20 -07:00
Alex Forencich
31901754a6 Add FMC pins to VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:55 -07:00
Alex Forencich
19a76cbaf9 Add FMC pins to VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:44 -07:00
Alex Forencich
72a35c08ef Clean up FMC+ pins on HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:19 -07:00
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
375b12865f Use QSFP Si570 for both QSFP modules on VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:00:33 -07:00
Alex Forencich
1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 11:05:24 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00
Alex Forencich
412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:34:53 -07:00
Alex Forencich
026a302c1c Use unified 10G/25G design for ExaNIC X25 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:45:47 -07:00
Alex Forencich
5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:42:40 -07:00
Alex Forencich
a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:40:38 -07:00
Alex Forencich
147435dfe1 Use unified 10G/25G design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:38:34 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00
Alex Forencich
0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:49:25 -07:00
Alex Forencich
489ee73355 Use unified 10G/25G design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:02:57 -07:00
Alex Forencich
729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:59:33 -07:00
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
b6a9092a9f Update makefiles for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:46:34 -07:00
Alex Forencich
c4376c8674 Update XDC files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:12:32 -07:00
Alex Forencich
905e6c6358 Add PTP timestamping tests for 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:35 -07:00
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:14 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9dafc3aaee Use internal BYTE_LANES parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:28:08 -07:00
Alex Forencich
9159425cd8 Use correct payload lengths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 22:18:50 -07:00
Alex Forencich
f705646e3e Pull out header size as a parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 15:48:39 -07:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-22 17:36:01 -08:00
Alex Forencich
5f15cdeb24 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:05:02 -08:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
db818b2f53 merged changes in axis 2023-02-17 16:03:28 -08:00
Alex Forencich
960a2eab61 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:56:40 -08:00
Alex Forencich
5f1ad94041 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-13 13:03:06 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 21:03:16 -08:00
Alex Forencich
c4f94773fa merged changes in axis 2023-01-29 21:03:02 -08:00
Alex Forencich
b81e323a6d Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 20:53:11 -08:00
Alex Forencich
3ac119305d Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 19:10:50 -08:00
Alex Forencich
e6d8ed7992 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 19:10:09 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 15:07:45 -08:00
Alex Forencich
450765187e Update lfsr.v 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 15:47:30 -08:00
Alex Forencich
7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 14:57:46 -08:00
Alex Forencich
f3d5e74527 Add RV901T example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 22:03:14 -08:00
Alex Forencich
713b138ece Fix timing of IDDR2 on Spartan 6 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 21:44:15 -08:00
Alex Forencich
a77c671920 merged changes in axis 2022-12-30 17:06:48 -08:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference) 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-29 23:54:17 -08:00