FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
1,123 Commits 1 Branch 0 Tags
Commit Graph

14 Commits

Author SHA1 Message Date
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
31901754a6 Add FMC pins to VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:55 -07:00
Alex Forencich
c4376c8674 Update XDC files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:12:32 -07:00
Alex Forencich
531f751e67 Update VCU118 XDC 2021-10-19 22:11:56 -07:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
306aa4db0b Update VCU118 XDC 2020-10-06 00:39:32 -07:00
Alex Forencich
b7c089dd22 XDC clean up 2020-07-13 23:58:30 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
05c6743473 Update xdc 2018-06-13 19:18:59 -07:00
Alex Forencich
f4d7edf23f Add VCU118 example design 2018-06-13 14:33:07 -07:00