FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
05770c5a1b Rework GT instances in VCU118 designs 2021-10-19 22:13:02 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00